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Hi kaz,
thanks for your response. The original constraint assigned by the MegaWizard for the SERDES was setup 3 and hold 3, is the hold multicycle supposed to be always one less than setup (for usual register-register transfers)?
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For a path where both registers are clocked by same clock, yes. This is purely an sdc definition.
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set_output_delay should not be necessary as far as I know, since I'm using dedicated hardware which reports a TCCS of 250ps, which is fine for my board and DAC.
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I don't get it. Either fpga or DAC or both should be responsible for io timing. You wouldn't need sdc constraint for fpga only if DAC is taking responsibility of io timing. Some devices do have automated data/clk alignment but you need to check that.
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Nobody asked me to invert the MSB, I figured it out when looking at the signals with a scope. I guess I wasn't clear about that: The inversion is for the first bit in every serial word, not the MSB of the DAC. So if my parallel input for one stream looks like 0101, the serial bits transmitted are actually 1101. This holds for every transmit LVDS pair. Strange enough, the receiver (ALTLVDS_RX) does not show this behaviour.
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This doesn't make any sense to me.
Honored Contributor
