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Altera_Forum
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12 years ago

Cyclone V 3v3 pins

Hello, My name is Jonathan, I am new with altera. I have a Cyclone V Development kit. I have connected a 3V3 input (from an UART) in a 2V5 pin (HSMA_D0 (K16)). I am going crazy becau...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks a lot for your replies.

I have a 50MHz clock in my state machine and I synchronize it when I detect a logical '1' in the input (start bit).

I have tested my design in a Zedboard and it works perfect (for ten hours). I think that I am doing something wrong with this FPGA.

I will continue testing it.

Regards,

Jonathan.