Forum Discussion
Honored ContributorCyclone V 3v3 pins
Hello,
My name is Jonathan, I am new with altera. I have a Cyclone V Development kit. I have connected a 3V3 input (from an UART) in a 2V5 pin (HSMA_D0 (K16)). I am going crazy because it works well but sometimes after a while it crash. I have checked everything with SignalTap (when it crash) and is like the design mutate. The behavior that I see does not make any sense. Do you think that the problem is the tension? Thanks a lot, Jonathan.7 Replies
Altera_ForumNo, the reason for the crash is not the because a 3.3V signal is being driven into a pin on a 2.5V I/O bank. Refer to the Maximum Allowed Overshoot and Undershoot Voltage on page 3 of the cyclone v device datasheet (http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf).
You need to continue looking for a fault in your code - or post something here for others to consider... Regards, Alex- Altera_Forum
Just a wild guess, but have you synchronized all inputs which drive state machine (in case you wrote UART module)?
- Altera_Forum
Thanks a lot for your replies.
I have a 50MHz clock in my state machine and I synchronize it when I detect a logical '1' in the input (start bit). I have tested my design in a Zedboard and it works perfect (for ten hours). I think that I am doing something wrong with this FPGA. I will continue testing it. Regards, Jonathan. - Altera_Forum
Have you synchronised the input via at least a double register to avoid meta stable states and glitches?
- Altera_Forum
I have inserted two registers betwen the input and the state machine and I think that now it works.
I have never used this kind of stages with Xilinx devices. Why do I need it with ALTERA? I want to understand the problem. I have another input/output three-state pad for an I2C. I have the same problem. I have inserted two registers between the input signal and the state machine and it has not solved the problem (It works but after a while it crash). Thanks a lot, Jonathan. - Altera_Forum
Async inputs need to be synchronised via a double register to avoid metastability and glitches in any system. You just got lucky in your Xilinx setup.
The other problem will probably be logic related. - Altera_Forum
Thanks a lot, now everything is working. I forgot to synchronize an interrupt signal.
I've gotten lucky for three years, because I've work with fpga (Xilinx) for the last three years. I don't know why but I never have problems with this. I will be careful even with Xilinx devices and I will synchronize everything. Thank you Tricky, I am very happy.
