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TonyK's avatar
TonyK
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3 years ago

Cyclone V 2.5V LVPECL vs LVDS inputs

When feeding an AC coupled LVPECL differential signal into a Cyclone V FPGA, the Cyclone V datasheet appears to indicate that DC bias and OCT 100 ohm differential termination is not available when As...
Core Logic
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago
Hi,
what are you trying to achieve? It's always possible to interface other differential IO standards to LVDS input, probably with the help of external hardware, e.g. termination resistors and passive level shifters.
  • TonyK's avatar
    TonyK
    Icon for New Contributor rankNew Contributor
    3 years ago

    My goal is to limit external components of the AC coupled differential LVPECL input signal to the GPIO pins. If I assign input as LVPECL I am limited to CLK input pins, and no on chip termination is provided or DC biasing for my AC coupled LVPECL signal. Datasheet does not appear to indicate Vid other than recommend when <700Mbp Vid for optimum performance: 0V to 1.85V (>700Mbps Vid 1V to 1.6V). In my application the signal is 160Mbps. By selecting LVDS input the LVPECL signal will receive the benefit of on chip 100 ohm termination and chip provided DC bias.

    Thank you for your feedback,

    Tony