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Altera_Forum
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12 years ago

Cyclone V - Interrupt Handling

Hello, i would like to know, how I can use interrupts in conjunction with a Cyclone V. (Comparative Avalon) Do you probably have an example for me? I would like to trigger an interrupt using a b...
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Altera_Forum
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11 years ago

On "2. Qn:": GIC may be programmed to Edge mode and you may not hold IRQ line from the FPGA in 1 longer than 1 tact.

And clearing of GIC pendig bits not clear IRQ line from the FPGA !

In Level mode interrupt handler MUST send a command to FPGA with clearing IRQ demand: GIC don't know about your hardware process.