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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone IV/EPCS config voltages

When using a Cyclone IV GX device with an Altera EPCS128 serial config flash (in AS mode), is there a preferred voltage for both the flash and the VCCIO of the configuration bank? Looking through the literature, I'm thinking 3.0V/3.0V might be the simplest option for avoiding any issues with voltage overshoot and overcurrent on the clamp diodes. The interfacing rules are mentioned in AN447, Table 1, however I'm not sure if the rules in that app note apply to the configuration pins or if those are a special case.

Also, I have the Cyclone IV GX Development kit, and they connect the EPCS device to 3.3V, but wire the VCCIO of the configuration bank to 2.5V. This seems to violate the Cyclone IV specs for 2.5V interfacing, which specifies a V(IH) Max of 2.8V. But the EPCS128, when powered by 3.3V, has a V(OH) Min of 3.1V. Granted they use a series resistor on the data pin, but if I'm reading it right, the dev board is always overdriving the FPGA by 300mV. Is this a bug or should I just trust the dev board schematic?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    should I just trust the dev board schematic?

    --- Quote End ---

    Never trust the evaluation board schematics, trust your own engineering judgement.

    Want more proof of this statement; look on the Cyclone IV Transceiver Starter Kit Embedded USB Blaster circuit on p12. The MAX II device is connected to the FTDI EEPROM USB_EECS/EECK/EEDATA signals. The EEPROM is powered from 5V, so those signals are 5V logic levels. I bet if you measure those signals on the MAX II which is powered from 2.5V, you'll find they are also violating the MAX II voltage specification.

    The same goes for the 5V LCD module. Try reading from the LCD and I'm sure you'll see close to 5V levels (many of the Altera boards have this design error). That will violate the Cyclone IV GX voltage spec.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If the EPCS chip is close to the FPGA and you have short tracks between the two then there is no problem using 3.3V for the configuration pins, there is very little risk of overshoot.

    IIRC the configuration pins don't have clamping diodes, and in that case there wouldn't be any problem driving them at 3.3V with a VCCIO of 2.5V. But if you can I think it's still a better habit to use the same VCCIO than the voltage you use on the I/O pins.