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Altera_Forum
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13 years ago

Cyclone IV power consumption during reset

I need to know the power consumption for a EP4CE55 FPGA during its reset state. I really can't locate this information, but it has to be written somewhere...

I intend to hold nCONFIG low until negotiation with the power supply is done, and startup is permitted. Does this seem like a valid way?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I need to know the power consumption for a EP4CE55 FPGA during its reset state. I really can't locate this information, but it has to be written somewhere...

    --- Quote End ---

    Try the PowerPlay EPE spreadsheet to get an idea (there's a spreadsheet for each device family).

    --- Quote Start ---

    I intend to hold nCONFIG low until negotiation with the power supply is done, and startup is permitted. Does this seem like a valid way?

    --- Quote End ---

    Ideally you should ramp the power supplies up within the timeframe recommended by the data sheet. The soft-start pins on linear and switching regulators can be used to make this happen easily enough. The datasheets generally indicate that if you cannot meet the power-on-reset sequencing requirements, then you should hold nCONFIG low until the supplies are ready.

    So yes, your scheme would work, though I would double-check whether it is necessary. For example, if you are providing an option to turn a supply on or off, or to select the I/O voltage, then you could turn all supplies off, program them to their new values, and then turn them on again.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks for your reply. I follow the powerup sequence, that should not be a problem. However, I'm not allowed to draw more than about 30 mA until power supply negotiation is done. I tried to run the EPA with no resources allocated, will this reflect the consumption in reset?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I doubt that your question can be answered by the power estimation tools. As far as the information isn't given in the datasheets (most likely not), making your own measurements is probably the best way to get an overview about the typical behaviour. Alternatively you can try to get a meaningful statement from Altera.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I'm not allowed to draw more than about 30 mA until power supply negotiation is done. I tried to run the EPA with no resources allocated, will this reflect the consumption in reset?

    --- Quote End ---

    Is there any reason you cannot use another device for power supply negotiation?

    For example, lets say this is a hot-swap board, or FMC module, or whatever it is that limits you to 30mA of power. You could use a microcontroller to negotiate the power with the main power source, and then that microcontroller can enable the hot-swap and power controllers to your FPGA. The microcontroller can then configure the FPGA. That same microcontroller can then monitor the power consumption and temperature of the FPGA and ensure it remains within spec.

    If you really can only use the FPGA, then as FvM comments, you'll need to measure the current yourself. You'll need to measure the power-on dynamics very carefully though, as for example, the Stratix II devices draw several times more current on their VCCPD pins before settling to their 'on' levels. This is not something you find in the data sheet - I only found it as I have over-current protection built into all my FPGA designs, and it kept tripping during power-on.

    Cheers,

    Dave