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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone IV PLL lock range: datasheet vs measurement

Hi,

According to the Cyclone IV device datasheet, the:

- PFD frequency (Fin/N) should range from 5MHz to 325MHz;

- VCO frequency (Fin*M/N) should range from 600MHz to 1300MHz.

When I measure these min and max values, by changing the M & N counters and monitoring the output lock signal of a reconfigurable PLL, I get:

- Fpfd(min) = 300kHz;

- Fpfd(max) not measured;

- Fvco(min) = 700kHz;

- Fvco(max) = 1300MHz.

-> Could anybody explain why the minimum measured frequencies are so far from the theoretical's (x10 factor for Fpfd(min), x1000 factor for Fvco(min))?

-> Is there an Altera document, which describes the "bandwidth 8x rule" stated by desert rat in his March 21st, 2007 post?

Here are the initial parameters of the reconfigurable PLL:

- Input frequency = 50MHz;

- C0 requested frequency = 30MHz;

- Primary clock VCO frequency = 600MHz;

- M counter = 12;

- N counter = 1;

- VCO post scale counter = 2;

- Bandwidth = 680kHz to 980kHZ;

- C0 post-scale counter = 20.

Thank you for your answers !

Regards,

DEx.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You see considerably lower minimal VCO frequency than specified in datasheet. I also observed that the unlocked free running VCO frequency is much lower than the specified minimal frequency. But

    - I'm not sure if it's realiably achieved for all devices across process, voltage and temperature variations

    - presumed, the actual minimal VCO frequency would be lower, it's obvious that the PLL filter isn't optimized for this frequency range. Higher phase jitter and locking problems may occur.

    I'm unable to locate the said 2007 discussion. Any reason why you didn't link it directly in your post?

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi FvM,

    Here is the discussion: showthread.php?t=138. I originally wanted to insert a link, but I was not allowed to do so, as I am still a Beginner!

    According to this rule, you will see that Fpfd(min) is lower (x10 factor) than the specified's, too.

    I could undertand a difference by a x10 factor between the specified and measured frequencies, taking into account the PVT variations , as you stated.

    But a x1000 factor regarding Fvco(min), I cannot. Moreover, that:

    - the output clock is really stable (frequency, duty cycle, edges, etc...);

    - the measured Fvco(max) corresponds to the specified's.

    -> Is the Fvco formula right?

    -> Does the lock generation logic take Fvco(min) into account?

    -> Any further idea?

    Thank you for your collaboration!

    Regards,

    DEx.