Forum Discussion
New Contributorcyclone iv PCB design
Frequent ContributorI think your query requires support from several subject matters experts.
I am here to help you on the voltage rails queries.
What voltage you need depends on what interface you are working with.
Example: If you connect to a chip that uses LVCMOS 3.3, then you use IO standard 3.3V. Then you need to power with VCCIO 3.3V.
There is a pin connection guideline that specify how you should connect your pins. And also a schematic review checklist to ensure you follow the guideline. Pasted the links below.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf
New ContributorThank you for your fast reply,
I have a further question related to IO. I noticed that DDR memories work SSTL IO standard which is about 1.2V and I know that I can change IO standard type in FPGA PinPlanner but how are these voltages are generated? do I need to generate them with external supply and connect the bank VCCIO to the supply I need to work with then change the IO standard type within the PinPlanner? or I can hook the VCCIO of all banks to a higher voltage for example 3.3V and then the FPGA internal circuitry takes care of generating the required voltage type? or there are specific voltages I need to connect the FPGA with( ex 3.3, 2.5, 1.2) in order to be able to generate all IO standards?
Thanks in advance
- JonWay_altera
Table 6-3 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf
...this will be helpful to your questions
It specify what voltage you should provide to VCCIO for every IO standard selection.
- mnasser431998
Thank you
