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Honored Contributor
Honored Contributorcyclone iv LVDS
Hi All, In one of our project we are using cyclone iv gx FGPA and AD9228 adc. Ad9228 operates and 1.8v and it has LVDS interface. FPGA's VCCIO is connected with 3v3. I hope this doesn't create ...
Altera_ForumHonored Contributor
Honored ContributorCyclone V FPGAs operating the LVDS I/O standard need the associated bank to be powered at 2.5V. This is the way Altera have chosen to power LVDS transceivers but isn't how all manufacturers have chosen to drive LVDS interfaces.
So, connecting your FPGA's LVDS interfaces (from a bank powered at 2.5V) to an LVDS interface on a device powered at 1.8V is fine. It is the LVDS standard that is important here, not the respective power rails. As for the 100Ω resistor - refer to figure 54 in the datasheet for the ADC. It identifies how they intend you to terminate the LVDS signal into the ADC. Generally, you will need a 100Ω termination anywhere that it is NOT built into the terminating receiver. Cheers, Alex
