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Altera_Forum
Honored Contributor
Honored ContributorCyclone IV GX PCIe SOPC design
Hello all, First I would like to inform you that I am new to this forum as I am to FPGA development. I am trying to create an FPGA based PCIe endpoint device using Altera's Cyclone IV FPG...
Altera_ForumHonored Contributor
Honored ContributorGood luck, this is one are where the documentation is simply not good enough.
Come on Altera, sort this out. :mad: I ended up working through a few example builds trying to derive a list of rules as to what should be connected and what shouldn't, but these weren't all consistent. There should be explicit rules in the user guide as to what all the ports should be tied to, or QSYS shouldn't expose them to the implementation victim. IMHO. Nial.
