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Altera_Forum
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15 years ago

Cyclone IV GX LVDS clock input resistor termination

Hi Altera experts, I am designing using the EP4CGX15BF14C8 (I have the transceiver dev board to try my design). Question I want a reference clock for the transceivers so I use a 125Mhz osc...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Looking carefully at the schematic of the Cyclone GX transceiver starter kit the ref clock that is LVDS is AC coupled and terminated off chip. But then there does not seem to be any attempt to restore the DC level (see c4gx_pcie_revb.pdf pages 5 & 6).

I guess if I copy this schematic I will not go far wrong.