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Altera_Forum
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15 years ago

Cyclone IV GX LVDS clock input resistor termination

Hi Altera experts, I am designing using the EP4CGX15BF14C8 (I have the transceiver dev board to try my design). Question I want a reference clock for the transceivers so I use a 125Mhz osc...
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Altera_Forum
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15 years ago

You need a termination resistor (see page 6-22 of the handbook):The LVDS standard does not require an input reference voltage, but it does require a

100- termination resistor between the two signals at the input buffer. An external

resistor network is required on the transmitter side for the top and bottom I/O banks.

page 6-28The LVDS receiver requires an external 100- termination resistor between

the two signals at the input buffer.

table 6-10 (volume 1) and table 1-5 (volume 2)

VCC_CLKIN for LVDS = 2.5V

Good luck, Ton