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LChen23's avatar
LChen23
Icon for New Contributor rankNew Contributor
4 years ago

Cyclone IV GPIO ,input in HDL, but leave float in hardware, must it set to week pull-up?

Hi' an GPIO ,set it to input in HDL, but leave it floating in hardware, I can sample it toggle in signalTAP if without week pull-up resistor. Why? shoul all this kind of input pin be set to...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I am not sure what exactly you are trying to do in your design. You can refer to these two sources on your design and let me know if you receive any errors:

1. Cyclone IV I/O Features: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf

2. Cyclone IV Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf

3. Cyclone IV Device Handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

Thanks