Cyclone IV E Speed Grad and Design Issues

It strongly depends on how the code is architectured. But basically each time a block needs inputs from several other blocks to produce an output, you need to be sure that both inputs are provided on the same clock edge, or at least that the output is only generated once both inputs are valid. The problem when you start to add pipelining is that you can have some data in one flow that arrives one or several clock cycles after the data in another flow, and if this is not properly taken into account, the block using both those flows as inputs will produce bad output.