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Altera_Forum
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8 years ago

Cyclone IV E Speed Grad and Design Issues

Hallo We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board wit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yes you probably need to be sure your data flow is correctly synchronized. Do you have a test bench for your component? It helps a lot seeing differences after a code change.