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Altera_Forum
Honored Contributor
Honored ContributorCyclone IV E Speed Grad and Design Issues
Hallo We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board wit...
Altera_ForumHonored Contributor
Honored ContributorYes exactly. You can start by looking for the longest combinatorial paths reported by timequest and see if you can change the code there, or add some pipelining.
