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Altera_Forum
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8 years ago

Cyclone IV E Speed Grad and Design Issues

Hallo We have a test hardware with the DE0 NANO Board which has the FPGA EP4CE22F17C6. The target Fmax for our design is 50 MHz and it can be achived in the FPGA thats on the DE0 NANO board wit...
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Altera_Forum
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8 years ago

hallo vlrean

thanks a lot for your detailed explanation. So it means when migrating the design to speed grade C8 from C6, we need to reconstruct our design to make sure that the desired Fmax is achieved.