ENava
New Contributor
2 years agoCyclone IV-E .sdc constraints for pin being both asynchronous and synchronous
Hi all!
I need to interface a Cyclone IV-E to an AD9915 DDS synthesizer.
AD9915 has a 32bit-wite parallel port that can be used both as:
- asynchronous address/data bus interface with read/write signals
- synchronous 32bit data input, clock sourced by AD9915 itself.
How can I write the fpga timing constraints?
In the asynchronous case I would specify set_false _path -to and -from all data/address and control lines, taking care of timings with fpga logic.
In the synchronous case I would create_clock coming from AD9915 and specify input_delay and output_delay according to setup/hold requirements.
But these two modes can be selected via a pin: they are mutually exclusive but both need to be addressed.
How can it be done properly?
Thank you!
Eugenio.