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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone IV E LVDS output voltage

Two questions:

1. According to Cyclone IV E handbook, the LVDS output level is 2.5V. So if a 3.3V is supplied to an I/O bank VCCIO, all the differential I/O pairs located in this bank can not configued as LVDS standard, is it right?

2. We have a fiber transmitter which is driven by differential PECL logic signals. From my understanding, the I/O pins of Cyclone IVE can not directly drive this transmitter. An extra chip is needed to convert a pin with LVTTLoutput (3.3V) or a pin pair with LVDS output to PECL standard. am I right?

Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Up to medium speeds, a pseudo-differential 3.3V ouput, level-matched by a resistor network may be an option.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks.

    Through testing, we find that FPGA can correctly output LVDS signals with 3.3V bank VCCIO input.

    The Cyclone IV E handbook requires that the pins can be configured as LVDS only with 2.5V bank VCCIO supply.

    I am not sure if the 3.3V LVDS can always work well.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The operation is beyond specifications and you can hardly expect a reliable statement about "always work". Maximum speed and voltage levels may be different.