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The rev B cable was updated to rev C to overcome this issue. The change was to move to a flex-rigid cable - the electronics in the USB-Blaster are unchanged.
So, you can get yourself a rev C cable and you'll be away. Alternatively, I suggest you shorten the ribbon cable on your rev B and you'll be happier, since won't have forked out for a new cable. I have several rev B cables all working happily with the new parts. See attached pic. Note - you don't need to go nearly as short as this!
Cheers,
Alex
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Thanks Alex, We have sort out the issue. Apparently there was a dry solder connection on the PCB and after applying some hot air on FPGA pins the problem disappeared :).
now The board works fine with "SOF" files but the FPGA won't reconfigure after power cycle. I have both JTAG and AS mode connectors on the board and tried both POF and JIC files to program the EPCS64 chip. The quartus programmer shows 100% success but reconfiguration doesn't happen after power cycle.
After some try and error, I noticed that if I left the JTAG cable connected to the AS header of the board (and connect the USB end to PC) the FPGA reconfigures successfully upon power up. I wonder if there is a Licence issue of some kind , even though my code is a simple counter program in verilog without any IP cores from Altera?
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