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Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- please let me know if you have any idea as yours design seems to work with cpld and fpga. --- Quote End --- You can try resetting the JTAG chain and the toggle TCK and assert TMS to bring the JTAG TAP into the Shift-DR sequence. The default contents of the DR register are the device ID code. Toggle TCK 32 times, and probe TDO. It should toggle - on all device outputs. Cheers, Dave