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Altera_Forum
Honored Contributor
15 years agoThanks for replay, FvM.
Actual MSEL configurations are Active Parallel (3.3V) for Master and Fast Passive Parallel Fast (3.3V) for next 4 slaves. Which was good for previous revision with parallel configuration. JTAG is configured in chain, as I mention before, Figure 9-26 in Chapter 9, Cyclone III Device Handbook, Vol 1. And, it sims to be JTAG is working. Autodetect in programmer showing a correct configuration and I'm able to configure the serial configuration device (EPCS64) by JTAG, as well as by AS Interface. The board is high density 16 layers board, as well as very expencive and I would like to debug other circuits on the board before next revision, what I can't do without programmed FPGAs. So, I will really appresiate for any help and ready to submit any information which can help.