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Altera_Forum
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17 years ago

Cyclone III problem with USB blaster JTAG communication

Hi all I've spent the last week debugging the jtag connection between the fpga and the usb blaster.:mad: I finally found something that is wrong.:) In JTAG there are 4 signals.. The fi...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Hi,

It looks like for some reason (bug) TDO and TDI signals are swooped on J4 pin header

(Cyclone III FPGA Starter Kit).

Again there are no pull-up resistors on TCK, TMS and TDI on the same cyclone III board.

In provided schematics for Cyclone III FPGA Starter Kit (sheet 8) when you track nets

CIII_TCK, CIII_TMS, CIII_TDI and CIII_TDO to "TOP LEVEL" (Sheet 3) you can see

nets CIII_TCK and CIII_TMS are not connected there.

Best Regards