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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone III pin assignment

Hi,

I want to build a custom board based on CYCLONEIII. In my system i have a parallel flash (config. of the FPGA) & DDR 167MHz clk & also some differential SSTL/HSTL_18,15 , and also some 3.3V devices which will talk to the FPGA.

Now i am running short of banks as i have to support various logic families.

I have some doubts regarding assigning Vref voltages to various banks,

  1. In the pin out excel sheet of CYCLONEIII they have mentioned the dedicated cinfiguration pins, which i cannot change. Also the address & few data pins for the Config Flash in AP mode are given as 'Optional/Dual-Purpose Configuration Pins', so does this mean that I can uses these pins for both flash interfacing as well as data & address pins for ddr. (ie during config they will be used for FLASH & after config. as DDR pins)

  2. In the pinout excel sheet they have given specific pins for DDR interfacing (DQ, DQS, DM pins), do i have to use these specified pins only for DDR interfacing or I can use any other IO pins?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    AP related dual purpose pins can be used for user I/O, if you don't intend to access the flash in user configuration. In this case, the flash could only be programmed by loading a dedicated flash loader configuration. Also the user logic connected to the pins must no disturb flash operation, e.g. not drive out unintentionally.

    The I/O standard used for DDR RAM address and data lines is obviously incompatible with a flash interface. I can hardly imagine, how they should share a pin.

    The requirements for DDR RAM I/O are discussed in various documents, e.g. the controller user guide and Cyclone III specific application notes. As a general answer: yes you have to keep a specific pin selection strictly, at least for DQ and DQS pins.

    You also should be aware of the distance rules when mixing voltage referenced and other I/O standards in a bank. At best, assemble a test design including the RAM controller, e.g. together with the Altera provided test driver, all pin definitions and typically some dummy logic to stimulate the pins.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi.. Can any1 send me the standard pin assignments of NiOS II Eval board(Cyclone III EP3C25)?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can copy the pin assignments from the example designs, e.g. from cycloneIII_3c25_start_niosII_standard.qsf.