Honored Contributor
Honored ContributorAP related dual purpose pins can be used for user I/O, if you don't intend to access the flash in user configuration. In this case, the flash could only be programmed by loading a dedicated flash loader configuration. Also the user logic connected to the pins must no disturb flash operation, e.g. not drive out unintentionally.
The I/O standard used for DDR RAM address and data lines is obviously incompatible with a flash interface. I can hardly imagine, how they should share a pin. The requirements for DDR RAM I/O are discussed in various documents, e.g. the controller user guide and Cyclone III specific application notes. As a general answer: yes you have to keep a specific pin selection strictly, at least for DQ and DQS pins. You also should be aware of the distance rules when mixing voltage referenced and other I/O standards in a bank. At best, assemble a test design including the RAM controller, e.g. together with the Altera provided test driver, all pin definitions and typically some dummy logic to stimulate the pins.
