Cyclone III max I/O frequency

Hi,

I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a

CylconeIII EP3C25(-8)

I want to provide this clock on a pll output pin with SSTL 2,5V standard.

In quartus II Version 7.1 I got this message:

Warning: Clock period specified for PLL output clock "pcixp_to_wb_top:g1x125|pxpll_altera:px_pll|altpll:altpll_component|altpll_b7q1:auto_generated|clk[2]" must be greater than or equal to 4.761 ns for output I/O "px_txclk"

Is it only possible to have 210Mhz on this output pin?

What can I do to solve the problem?

regards

cyclone