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Altera_Forum
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15 years ago

Cyclone III EPC120F484C8 LVDS speed

Hi, I'm planning to use a Cyclone III EPC120F484C8 to read the data from an ASIC. The ASIC has 50 parallel output bits (25 LVDS pairs read using clock A, and 25 more using clock B) at a continu...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Yes, the maximum interface speed is 402 MHz. But clocking the datapath at 200 MHz already restricts the complexity of logic and arithmetic operations, that can be performed in a single clock cycle. But that's a matter of core performance rather than I/O speed.