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Altera_Forum
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15 years ago

Cyclone III EPC120F484C8 LVDS speed

Hi, I'm planning to use a Cyclone III EPC120F484C8 to read the data from an ASIC. The ASIC has 50 parallel output bits (25 LVDS pairs read using clock A, and 25 more using clock B) at a continu...
Altera_Forum's avatar
Altera_Forum
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15 years ago

You didn't read the manual thoroughly. 275 MHz restriction is for emulated LVDS only. But it would be still above 200 MHz, so I wonder what you are actually asking for?

The said device has a sufficient number of differential input pairs, everything else is a matter of detail design.