Cyclone III Dev board fitter failure when using SRAM

Hi,

I am using a Cyclone III EP3C120 Dev board and am having trouble with the fitter when I try to run the I/O Assignment Analysis while using the board's SRAM - it says that there are too many outputs on the VREG group (please see the attached figures). I have made sure that the data bus that is failing is part of an 'Output Enable Group' and I am at a loss for why the fitter is failing, the design appears to be below the 20 allowable outputs for the VREF group.

The SRAM has a 32 bit data width and is on a shared bus with the board's flash module. I am using the 'Tri-State Conduit Pin Sharer' to share the data and address buses between the flash and SRAM (QSys figure attached).

Any help or suggestions would be greatly appreciated!Thanks!