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Altera_Forum's avatar
Altera_Forum
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10 years ago

Cyclone III Critical Warning (15534) illegal output frequency must be less than 472.

Hi

I am getting the following message from the quartus II :

Critical Warning (15534): PLL clock output sys_pll_40to100:sys_pll_40to100_inst|altpll:altpll_component|sys_pll_40to100_altpll:auto_generated|wire_pll1_clk[0] feeding the core has illegal output frequency of 500.0 MHz that must be less than 472.6 MHz

Is there a way to output a 500Mhz clock on any of the cyclone III I/O pins

Thanks in advance

Ronen

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The cyclone iii device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf) - PLL Specifications on page 1-15 - specifies the maximum PLL output frequency of 472.5MHz. So, no - the tools aren't going to allow you to do what you're trying.

    You can try building a PLL with the ratios you want but specify a lower input clock frequency. That way you'll keep the tools happy. You can then go on to drive the PLL at the frequency you want to achieve 500MHz. However, the max parameters in the datasheet are there for good reason. I'm not sure I'd expect your 500MHz output signal to look (at all) good or be particularly usable.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Alex

    Thank you very much, was looking for these specs. and some how missed them.

    Thanks for the suggestion on how to "fool" the quartus, not sure I will take the risk and try it.

    Al the best

    Ronen