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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone III counter problem

Hi all, I seem to have a problem with a counter implementation in Cyclone III. The code is attached below. Bascially, it should generate '1' for 1 clk cycle on parallel_load2 whenever the CNT i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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As shown here, the counter value was updated from 241 to 242 on the falling edge of ClientRxRClk. I was thinking maybe there's glitch from my external clock ClientRxRClk, but signalTap II doesn't show this.

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SignalTap acquisition clock frequency is too low to reliably show glitches.

Ringing clock edge sounds quite plausible. Usually source side impedance matching will remove ringing.