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Honored Contributor
Honored ContributorCyclone III counter problem
Hi all, I seem to have a problem with a counter implementation in Cyclone III. The code is attached below. Bascially, it should generate '1' for 1 clk cycle on parallel_load2 whenever the CNT i...
Altera_ForumHonored Contributor
Honored ContributorI am suspecting that the RxRClk signal from the external chip might not be as clean as it should be. Therefore, it might have some ringing on the fall edge creating the FPGA to update twice. Is there a way to prove this theory? if this is the case, what can I do? I know about debuncing circuit for switch, but never heard of clock signal needs to be debunked.
