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What I mean is that can your board( or your FPGA) run after pof being downloaded?
You pointed that your jtag is ok in your last post, so if your fpga can't run with your pof, you should double check the interface between EPCS and fpga. You know the jic file is downloaded thru the jtag and a "bridge" between epcs64 and fpga, you must confirm that the jtag and the bridge should be both ok.
So if your fpga can run with pof, the "bridge" interface should be ok. pls check the interface between the epcs64 and fpga firstly.
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thanks,the fpga can't run with pof file.
I also suspect the interface between epcs64 and fpga is not ok,but the board has been finished and can't be changed easily.
so whether the epcs64 is away from fpga when wiring?
can this condition result in the epcs64 can't be read normally by fpga?
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