Cyclone III Configuration Corrupts !..

Is this a development board, or a fresh, just-built board?

If it is a development board, it is possible that you have the EPCS16 configuration set improperly. The page for this is hidden in the assignments, under device, then under device and pin options. The settings should look probably be active serial (can use configuration device), EPCS16. You may need to also have the generate compressed bitstream button clicked.

If it is a new board, there could be quite a few things wrong. You could be missing pullups (check the Altera configuration app note). If the tracks between the configuration device, programming header and FPGA are particularly long, you can also end up with ringing on the clock line, but I've only seen this on really bad layouts. In general, the Altera parts are very forgiving.

I guess you should also check the obvious: make sure that the part on the board matches the part selected under Assignements->Device.

Good Luck

Are you programming the EPCS device with the Quartus programmer? Do you have JTAG access to the FPGA? If so, can you program the FPGA via JTAG? Have you checked the signals between the FPGA and EPCS device (DCLK, DATA) for signal integrity issues?

There is an option in Quartus Settings/Device and Pin Options.../General Tab called "Auto-restart configuration after error". If you uncheck this option does it just try to configure once per power cycle?

i have solved the problem, it was because of a 100pF capacitor which was parallel to the pull up resistor of CONFIG_DONE pin.

i removed it and everything looks fine now.

anyway, thanks very much.