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Altera_Forum
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14 years ago

Cyclone III and EPCS4

Hi, i am trying to start Cyclone III with EPSC4. I write VHDL code wich toggles one of FPGA pins, but nothing happens, Quartus is programming the flash device - programmer says that everything is ok, i can sniff clock signals on usb blaster connector, when i trying to start board without USB Blaster, and power up - nothing happens, there is no clock on DCLK, how i can debug this? Maybe there is mistake in my schematic? (schematic attached). Please help me.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The schematic looks correct.

    It seems very odd that there wouldn't be any activity on the DCLK line. I would suggest monitoring other lines, such as nSTATUS for activity. I would expect nSTATUS to change independent of MSEL. A review of how you are looking at the signals may also be productive. ie: The signals are toggling but not being detected.

    The application of LED's on U51 seems odd. First, the polarity of the LED's test appear backwards. Next, no current limiting resistors. Lastly, what use are they in general?

    Another potential issue may be in the selection of the correct EPCS1SI8N. There appears to be 2 speed grades, 20 and 40 MHz. The Cyclone three needs the 40 MHz version. I'm still sorting out how to distinguish between the two version with the markings on my devices. See PCN0514.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i remove diodes, i check pins with oscilloscope up to 200MHz, i connect oscilliscope to nSTATUS and CONF_DONE and nCE, when powers goes up - nothing happend, everything is on 0V level

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    yes it is, sory i say wrong, on CONF_DONE i have about 700mV and 630Hz 200mV peaks ;s

    EDIT: new symptome, at beginning system connects only 3.3V bus, when it is done CONF_DONE looks like in attachment, then 3.3V is off, and then all supplies are on togheter, in these last step - there is everywhere 0V (CONF_DONE nSTATUS nCE)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Is the exposed pad of the Cyclone III connected to ground?

    --- Quote End ---

    I also thought about this point, it's explicitely shown in the schematic. I wonder, if the pin is also known to be soldered correctly?

    --- Quote Start ---

    at beginning system connects only 3.3V bus, when it is done CONF_DONE looks like in attachment, then 3.3V is off, and then all supplies are on togheter

    --- Quote End ---

    I'm not sure, what you are describing here. Is it about a irregular power-up sequence?

    According to the hardware manual, schottky diode should be used as AS clamp diodes, I assume that the LED symbols have been used by mistake.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    leds are becouse of appropriate footprint, i resolder FPGA again, and there are different symptomes - after all supplies are on, DCLK is 3.3V, CONF_DONE is 3.3V, nCE is 3.3V, nSTATUS is 0V, and on all IO pins is 3.3V, still no clock on DCLK,

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    SOLVED! in docs is write that nSTATUS will up when FPGA discover three supplies - VINT VCCA and VCCIO of bank 1. They didnt mention that all of VCCIO should be connected - when connected missing 1.8V VCCIO everything works like a charm.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    They didnt mention that all of VCCIO should be connected

    --- Quote End ---

    See POR chapter in Cyclone III hardware manual. In your design, both bank 6 and 7 are driven from 1V8 volt.

    --- Quote Start ---

    Cyclone III device family contains POR circuitry to keep the device in a reset state

    until the power supply voltage levels have stabilized during power up. During POR,

    all user I/O pins are tristated until the VCC reaches the recommended operating levels.

    In addition, the POR circuitry also ensures the VCCIO level of I/O banks 1, 6, 7, and 8

    that contains configuration pins reach an acceptable level before configuration is

    triggered.

    The POR circuit of the Cyclone III device monitors the VCCINT, VCCIO, and VCCA pins

    during power-on. The enhanced POR circuit of the Cyclone III LS device includes

    monitoring VCCBAT to ensure that VCCBAT is always at the minimum requirement voltage

    level.

    --- Quote End ---