Cyclone III and DDR2 SDRAM DQ Pin Groups

In the Cyclone III Device Handbook, it says that the EP3C120 can have 6, x8 DQ groups. The Terasic Cyclone III PCI-X Development board can use a 4GB SO-DIMM with 64 DQ lines. How can you get 64 DQ lines if the part only supports 6 groups of 8, which equals 48, not 64. Any one have an idea how this could be possible? Are they mixing the top with one of the sides? i don't think that is recommened.

I would like to implement the same concept in my design by using a 4GB, SO-DIMM using a Cyclone III and using either the top or the bottom I/O-bank to do so. Any thoughts or suggestions is greatly appreciated!

Thanks!