Honored ContributorHi all,
I just found out that the Cyclone III 120 pins have full 3.3 volt IO, but when I migrated to 80 pins. I lose power IO drive strength from my pins (2.3 volt), so I couldn't run my SDRAM clock speed. Did I get bad FPGA EP380 or the way Altera design? I have try 8 boards with EP380 at my work place. They are the same losing power IO to SDRAM memory. Best regards, Sean
Honored ContributorWhat package are you using.. Are you sure all the VCCIO pins for the C80 are connected to 3.3 and not something else?
With Altera, when migrating between device you need to double check all three device IOS. Although most are identical, some pins are reserved for power/ground in particular family members while others may be NC. If you have an old IO assigned, and it's expecting it to be a VCCIO that could cause problems like you are describing. Or if it's a new board, make sure the VCCIO is actually at 3.3 instead of 2.5. PeteHonored ContributorDo you mean, that the drive strength settings (in pin planner and fitter report) are identical, but the actual strength is different? Or Quartus inforces a different setting? In the first case, you should consider, that the process variation between slow and fast corner is about 2:3 according to IBIS files. Different production lots may be near to either corner values at worst case.
Honored ContributorThanks all.
It's problem with SDRAM clock is so low on EP3C80 (2.3 Volt). Hardware engineer puts temp fix is to put 150 Ohmz resistor to drive the clock up. I tried to set max in drive strength option, but it doesn't work. I don't know why the board EP3C80 has lower volt than my other board EP3C120. My hardware engineer will look into it. Best regards, Sean
