Cyclone III & SDRAM

Hello everybody.

the situation:

we have Cyclone iii(EP3C25Q240C8) and sdram(MT48LC4M16A2) are connected directly. Clk from board 24MHz plled to 100.

need to do : write data block to RAM and read it back

for testing was created easy contour - inclk to pll and then to counter(data imitation), to driver(make control signals) and to SDRAMcontroller. After the SDRAM data goes through Controller to 1port ram in FPGA(view the data).

Thats looks easy but something goes wrong coz it works ONLY then DQ bidir pin was added to signaltap otherwise it doesn't. We try 3 different SDRAM controllers and try to write source code in VHDL and AHDL - the same.

very need a solution for that problem, previously thanks.

Project file i will attach below