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Honored ContributorCyclone III & SDRAM
Hello everybody.
the situation: we have Cyclone iii(EP3C25Q240C8) and sdram(MT48LC4M16A2) are connected directly. Clk from board 24MHz plled to 100. need to do : write data block to RAM and read it back for testing was created easy contour - inclk to pll and then to counter(data imitation), to driver(make control signals) and to SDRAMcontroller. After the SDRAM data goes through Controller to 1port ram in FPGA(view the data). Thats looks easy but something goes wrong coz it works ONLY then DQ bidir pin was added to signaltap otherwise it doesn't. We try 3 different SDRAM controllers and try to write source code in VHDL and AHDL - the same. very need a solution for that problem, previously thanks. Project file i will attach below4 Replies
Altera_ForumYes, you have to use the values read back otherwise there is no need to store them.
- Altera_Forum
I try that, "do xor with all the bits and then output the result to a pin"
so, now 1port ram have random values, but oscilloscope view only blocks "Controller => Ram", thats mean data still don't read( or not write?) Add project file to 1st post - Altera_Forum--- Quote Start --- I suspect the read data-path has been optimized out. Quartus II is quite intelligent about that, e.g. even if you connect a RAM to the read-data output from the SDRAM controller, but no logic is reading that RAM QII will optimize the complete chain away. --- Quote End --- Yup -- do something with all the bits from each read and then output the result to a pin. XOR will do.
- Altera_Forum
I suspect the read data-path has been optimized out. Quartus II is quite intelligent about that, e.g. even if you connect a RAM to the read-data output from the SDRAM controller, but no logic is reading that RAM QII will optimize the complete chain away.
