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Altera_Forum
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14 years ago

Cyclone III & SDRAM

Hello everybody. the situation: we have Cyclone iii(EP3C25Q240C8) and sdram(MT48LC4M16A2) are connected directly. Clk from board 24MHz plled to 100. need to do : write data block to RAM and re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I suspect the read data-path has been optimized out. Quartus II is quite intelligent about that, e.g. even if you connect a RAM to the read-data output from the SDRAM controller, but no logic is reading that RAM QII will optimize the complete chain away.

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Yup -- do something with all the bits from each read and then output the result to a pin. XOR will do.