Cyclone III + EPCS + Remote Update

I am using the ASMI block. I ported the Altera code and added a state machine to interface to my code.

So, I realized I did not have the latest user guide for the Megafunction. I downloaded that and see that Altera now lists the max clock freq for each device. For a Cyclone III it is 40Mhz.

The new UG also includes an update to the READ_SOURCE table which shows a value of "11" as being the input register. That makes sense looking at the block diagram provided in the Cyclone datasheet since READ_SOURCE appears to be a mux select for the readback path.

Also included is an updated table of operations which is helpful too.

RTFM right?

Next up is to move a new image into FLASH and hit the reconfig pin.

Thanks

Kevin.

Hi

I am using EPCS controller built using SOPC builder(Q9.0), FPGA device is Cyclone III and configuration device is EPCS16. I am using external processor to communicate with EPCS16 via Avalon Master, SOPC Fabric and EPCS controller (NIOS is NOT used).

I have user logic state machines written for factory and application image configurations.

I have simulated/verified Data transfer from my remote update logic to ASMI megafunction & EPCSmemory model u.

I have one question:

I have included Remote update controller & EPCS in the SOPC builder while generating the system.

Do I have to include ASMI in the SOPC builder while generating the system?

Greatly appreciate your time!

Thanks,

Brunda

In SOPC builder,now,I have Remote System Upgrade(RSU) and EPCS.

Both connected to NIOS.

But,how do I connect RSU and EPCS in SOPC builder?

When I use the RSU megafunction-cycloneIII ,it doesn't have ASMI ports to connect to ASMI.

So,how does rsu communicate with epcs (to load factory configuration from epcs)?

I am using EPCS controller built using SOPC builder (Q10.0), FPGA device is Cyclone III and configuration device is EPCS16.

I have user logic state machines written for factory and application image configurations.And,an image update logic to load new image through ASMI.

Brunda:

Double posting is not good, it's confusing to someone seeking an answer and having to read the same question multiple places, but the answer in a single place. PLEASE do not double post.

Your answer is here:

http://www.alteraforum.com/forum/showthread.php?t=18610&page=7

Basicaly: you do not need to connect the RSU and you do not need to connect the EPCS. But you do need to write software for them.

Thanks for your reply.I didnt realize that I have posted my question twice.

Sorry for the inconvenience.

Can you please point me any document which describes the software needs to be written for these blocks to work.

Thanks again.

The link to the grigaitis website has been useful for me, but I only managed to get the remote update working after I added a delay as follows:-

IOWR(remote_update_base, 0x4, reconfig_offset >> offset_shift);
// *** delay added ***
delay_us(100);
// Perform the reconfiguration by setting bit 0 in the
// control/status register
IOWR(remote_update_base, 0x20, 0x1);

The delay routine is my own crude for() loop, so I'm not sure how long I *really* needed to wait ... but it works for me !! :)

It may be due to me using a full NIOS core running @ 40MHz ... who knows !?!

I am using EPCS controller built using SOPC builder(Q9.0), FPGA device is Cyclone III and configuration device is EPCS16.

I have user logic state machines written for factory and application image configurations.

I have simulated/verified Data transfer from my remote update logic to ASMI megafunction & EPCSmemory model.

I am using EPCS,ASMI 7 remote sys upgrade mega functions.I didnt use them in SOPC builder.

Now,I am trying to program FPGA using jic file which is converted from sof file.It wont let me program without SFL(Serial Flash Loader.)

How I can avoid using the SFL in my application?

Looking forward for your help!

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It's been a while, so I don't remember all the details.

I added a "Remote Update Controller" in SOPC builder. To trigger the reconfig, you then do something like this:

// set address
IOWR(CYCLONEIII_BASE, 0x04, nAddress >> 2);
   
// disable watchdog timer
IOWR(CYCLONEIII_BASE, 0x03, 0);
   
// reconfig
IOWR(CYCLONEIII_BASE, 0x20, 1);

In my case, I was only using internal block RAM for my NIOS code. Therefore, I did not have a seperate ELF file to worry about as all my code was included in the SOF file. I used the sof2flash utility to generate a S record file which contained the data to flash to the EPCS.

--- Quote End ---

Hi, kevin

Would you tell where theses code locate? In factory nios program or application nios program? I'm now very confusing with this issue. I want to figure out the reconfiguration process.

Thank you in advance!

-wei

Hi fifamanutd, this code is an example code to configure and trigger the reconfiguration. You can use the remote_update core on both images (same for the code) if you want to switch between imagens whenever you feel like, but you need to have it at least at factory image...

Try reading the Remote Update Megafunction User Guide and the SOPC Remote Update user guide (Embedded Peripherals IP User Guide).

Cheers

Hi wgutstein,

Thank you for your reply. I just figured all my questions out and realized a remote update system in my board yet.

Thank you all.