Forum Discussion
Honored ContributorCyclone III + EPCS + Remote Update
As the title suggests, we want to implement the remote update feature using the CIII and (Active Serial) EPCS64 device. The objective is to get two application programs stored on the EPCS device, both fpga bit configuration as well as the nios software.
I've searched this site for info on a complete start-to-finish solution that someone has already had success with. Altera has app note AN521 (http://www.altera.com/literature/an/an521.pdf), but it is specifically for the Active Parallel design. Does Altera have a similar document for Active Serial devices? Or have they discovered that it is impossible to this with EPCS devices and aren't spreading the word?20 Replies
Altera_ForumI have successfully implemented a system which uses remote update with active serial configuration.
Altera's documentation definitely seems lacking in this area. I got it working based on AN429 and the Cyclone III handbook. A scope on the SPI lines to the memory and other configuration related signals was also a big help. In the end, I created my own SPI component and software for writing and reading to the flash memory. The tricky part was then figuring out how to control the remote update hardware to trigger the reconfig to the application image.- Altera_Forum
"""The tricky part was then figuring out how to control the remote update hardware to trigger the reconfig to the application image."""
Hi kevin how did you achieve reconfiguration successfully...cause am right now stuck in this thing... please tell whether you converted the application elf file to flash and then to binary ....and then did you flash this binary to the location and triggered reconfiguration... and also please let me know the steps for reconfiguration.... any help would be highly appreciated... thanks a lot in advance - Altera_Forum
It's been a while, so I don't remember all the details.
I added a "Remote Update Controller" in SOPC builder. To trigger the reconfig, you then do something like this:
In my case, I was only using internal block RAM for my NIOS code. Therefore, I did not have a seperate ELF file to worry about as all my code was included in the SOF file. I used the sof2flash utility to generate a S record file which contained the data to flash to the EPCS.// set address IOWR(CYCLONEIII_BASE, 0x04, nAddress >> 2); // disable watchdog timer IOWR(CYCLONEIII_BASE, 0x03, 0); // reconfig IOWR(CYCLONEIII_BASE, 0x20, 1); - Altera_Forum
Any clues if altera will update AN379 ?
It still does not use some of the new features of the ASMI megafunction, and would be a good basis to start a RSU system without NIOS. - Altera_Forum
I got a confirmation from Altera that AN379 is outdated and one should use ATLASMI_PARALLEL instead
- Altera_Forum
Try this: http://www.grigaitis.eu/?p=514 it worked to me.
- Altera_Forum
Hello - I have a question about using the RSU core as well. Same situation, I am using a Cyclone III & EPCS w/ Remote Update except that I am not using a NIOS core, just user logic to both update the FLASH (via PCI) and to configure the RSU macro and enable re-config.
So, everything is in place and appears to be functioning OK, I have an image that includes signal tap and can see many of the internal signals. When I do a write to param "100", I get a BUSY indication back from the core. When BUSY goes away, I do a read of param "100" and again see the BUSY signal asserted but the data returned is always "00000000". I have the RD_SRC set to "00" for both the write and read - according to the liturature, this is supposed to be the current state contents in the status register. If I keep walking through addresses, I can see the data I wrote to param "100" with RD_SRC = "00" show up at param = "100" but the RD_SRC = "11". Any thoughts on this behavior? I am running w/ a user clock of 33Mhz and can see no limitatons for it's speed. Does anyone know if there is a maximum clock freq that can be used with this core? Thanks Kevin. - Altera_Forum
Though I don't recall, exactly, I "think" that altremote_update has a limit of 25MHz...at least on CIII, that is. Go take a look at the Application Selector design for the NEEK and you'll see what the requirements are....with a Nios II, of course.
You know, you could go with the Nios II/e. It's now completely free, includes source code, and takes up hardly any resources. Cheers, -slacker - Altera_Forum
Slacker - thanks for your response, I did try this with an 11Mhz clock but see the same behavior.
I am running with the image loaded from sector 0x0 so I believe I am in Factory Config mode and since the data I write does come back on a read... albiet from the wrong address, it seems to be accepting the write. I just don't understand why I can't read from the offset that I am writing. Thanks Kevin. - Altera_Forum
Hi Kevin,
What are you using to read/write to the EPCS (SPI flash)? I've only ever used the epcs_controller in an SOPC Builder system with Nios II. Doing it this way, I read/write to the EPCS using the epcs_controller and use the altremote_update block to trigger appropriate resets... Regards, --slacker
