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So, my worry is that the RAM used by FFT core may be overlapping with the memory I used to store the data. My data may be overwritten by the FFT core during the computation if this is the case.
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That won't ever happen. There's no way how internal memory can be shared between multiple design blocks, it's always instantiated exclusively. You are apparently imagining FPGA block RAM as a resource similar to processor RAM connected through a common bus. Each FPGA RAM block has it's own data and address lines that are individually connected to logic.
If you actually want to time share memory in special situations (very unusual) you need to define explicit multiplexers.
You can review the Compilation Report/Fitter/Resource Section/RAM Summary for the RAM usage in your design. The same information is also in the Project Navigator/Hierarchy display.
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