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Altera_Forum
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18 years ago

Cyclone II I/O Output at Power Up!

Using a EP2C8F256C6 and found that during power up there is a 3.3V pulse coming out from the I/O pins. Pulse lasts for ~10ms.

As I understand, during power up, pins should be tri-stated but I'm still seeing the output.

Tried to isolate the problem thinking it was another device but seems that the output is coming from the FPGA.

Has anyone experienced this before? Need help.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The i/o are really tri-stated at power-up, reset, configuration and initialization (to be verified).

    In cyclone II device, there are a weak pull-up resistors(~25kOhms) wich pull the pins high.

    See datasheet and "configuration handbook"

    Except for some pins :

    dev_oe which goes low (open drain) until the first data configuration frame comes. If you use dev_oe as an user I/O pin.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    All IO Pins of an unprogrammed device should be Tri-stated with a weak pull up. (cf. Cyclone II Handbook - Feb 08 - p. 1-3) So if you do not have a pull down at the pins you will see the pins go up to 3.3V.

    The pull up values are given in Table 5-3 of http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf - there is also a suggested value for a pull down resistor in there.

    Regards,

    Lokla
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    You have to configure the unused pins as input tristated. At power-up they won't produce any output signal.