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Honored Contributor
Honored ContributorCyclone II ESD Problem
Hi there, We are experiencing very strange behavior of the FPGA (EP2C5T144C8) when conducting ESD tests according to IEC 61000-4-2. During the indirect discharge test, the FPGA freezes and all ...
Altera_ForumHonored Contributor
Honored ContributorI imagine that the observed global latchup can be only triggered by pushing a supply line beyond rate voltage range. Sufficient bypassing and additional transient suppressors if necessary should help.
Where do you apply the ESD discharge?
