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Altera_Forum
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12 years ago

Cyclone II ESD Problem

Hi there, We are experiencing very strange behavior of the FPGA (EP2C5T144C8) when conducting ESD tests according to IEC 61000-4-2. During the indirect discharge test, the FPGA freezes and all ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Since it requires a power cycle to come out of this condition, it sounds like you are getting it into a latchup condition.

I've never seen this particular issue, with the Cyclone II, but that doesn't meet it doesn't exist.

Have you tried to wiggle the IO's with jtag boundary scan? Also does the current draw of the part go up (for the IO banks) when it's stuck in this condition?

I've seen EDS testing destroy IO's, but that usually is destructive and non-recoverable.

Pete