cyclone II decompression rbf

Hi Petr:

Although the compression algorithm used is probably one of the standard ones, I doubt it's published anywhere other than internal Altera Documents.. (FPGA manufacturers tend to keep the details of the bitstream proprietary)

It sounds like you are using a micro for in field updates. If that's the case, have you ever thought of just having the micro program the bitfile every bootup. (through either jtag or passive serial modes)

You can punt the EPCS1 then, and have bitfile just stored in the micro's flash.

Pete

--- Quote Start ---

Hi Petr:

It sounds like you are using a micro for in field updates. If that's the case, have you ever thought of just having the micro program the bitfile every bootup. (through either jtag or passive serial modes)

You can punt the EPCS1 then, and have bitfile just stored in the micro's flash.

--- Quote End ---

We've developed a CPU board which has AVR32 + CYCLONE II + EPCS1 + SPI FLASH. All is for industry temperature range and we will used it as common board for many different products (our ones).

The CYCLONE II (does tasks which are time-consuming for MCU)

- ethernet tasks (fiber phy, packet filtering)

- more peripheral for CPU: I2C, SPI, UART

Idea to use EPCS1 is only to keep boot time as low as possible.

- FPGA is booting standalone via ECPS1

- CPU is already doing some task (when FPGA is not configured) and this save time

I want to use JTAG connection to FPGA from MCU to testing purposes from MCU when manufacturing . After testing it is used for configuration FPGA directly (when boot time is not requried fast) or to upgrade EPCS1 via FPGA's JTAG. Of course I can connect pins not to FPGA's JTAG but to EPCS1, but this is not my situation (pin usage saving, board design, etc.)

Only problem want I have unsolved is that, I have same configuration but i need two images - compressed and uncompressed. And this is needed only because JTAG accept uncompressed image but EPCS1 requires compressed one. I would like to do only one these operations

- compress image inside MCU or

- uncompress image inside MCU

to reduce two images to one only inside MCU.

I read patent US8,427,347 but it seems there is a much easier compression used by CYCLONE II.

---

The second problem is: I'm unable to compile ENHANCED SFL into EP2C5 - the compiler is stopped with no warning or error [Quartus II 12.0sp2 Web Edition] and CPU load goest to 100%. If I unchecked ENHANCED SFL, the compiler works. But this is minority problem for me.

Petr

How about using the 4 Mb chip EPCS4 or an equivalent Serial NOR Flash (M25P40), and just leaving the bit stream uncompressed... It will take longer for the FPGA to program, but will still probably be done before your CPU is ready. If you are using true EPCS parts, it's probably cheaper to go to the larger M25P40 device.

That way you only have to use the uncompressed bitstream.

Pete

Pete

--- Quote Start ---

How about using the 4 Mb chip EPCS4 or an equivalent Serial NOR Flash (M25P40), and just leaving the bit stream uncompressed... It will take longer for the FPGA to program, but will still probably be done before your CPU is ready. If you are using true EPCS parts, it's probably cheaper to go to the larger M25P40 device.

That way you only have to use the uncompressed bitstream.

--- Quote End ---

Yes, this is only possibility how to make workaround if there is no description about how is compressed/decompressed bitstream. Thank you for support! I want to be sure that tehere is no documentation about compression.

I did a quick test, where

EP2C5 is in PS config mode

AVR32 is connected to SST25VF032Bvia SPI interface, and NCONFIG,NSTATUS,CONF_DONE

SST25VF032B CLK and DOUT is connected parallel to DCLK and DATA0

SST25VF032B has stored image with LSB first in each byte

And I did

-NCONFIG=0

-sending reading command to SST25VF032B

-NCONFIG=1 and wait for NSTATUS=1

-continue in reading of SST25VF032B for size of bitstream

-and wait for CONF_DONE

-after CONF_DONE (EP2C5 - USER MODE) the SST25VF032B can be used by AVR32 for normal operation.

This works too. And no EPCS is needed. It is fast as possible even controlled of MCU (AVR32) - only clock during configuration needed after initiating reading of SST25VF032B.

Question:

- ALTERA says that both pins DCLK and DATA0 should be connected to VCC or GND in PS configuration when is USER MODE (after CONF_DONE)

- I read this ALTERA statement as pins should not be floating and it doesn't matter if pins have 1 or 0.

- Does can anything happend to EP2C5 when I toggling its DCLK and DATA0 during USER MODE by external AVR32? (A reason why I need this, that SST25VF032B is connected in parallel with these pins)

I did a test it seems nothing happends, but no confirmation by documents.