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Hi Petr:
It sounds like you are using a micro for in field updates. If that's the case, have you ever thought of just having the micro program the bitfile every bootup. (through either jtag or passive serial modes)
You can punt the EPCS1 then, and have bitfile just stored in the micro's flash.
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We've developed a CPU board which has AVR32 + CYCLONE II + EPCS1 + SPI FLASH. All is for industry temperature range and we will used it as common board for many different products (our ones).
The CYCLONE II (does tasks which are time-consuming for MCU)
- ethernet tasks (fiber phy, packet filtering)
- more peripheral for CPU: I2C, SPI, UART
Idea to use EPCS1 is only to keep boot time as low as possible.
- FPGA is booting standalone via ECPS1
- CPU is already doing some task (when FPGA is not configured) and this save time
I want to use JTAG connection to FPGA from MCU to testing purposes from MCU when manufacturing . After testing it is used for configuration FPGA directly (when boot time is not requried fast) or to upgrade EPCS1 via FPGA's JTAG. Of course I can connect pins not to FPGA's JTAG but to EPCS1, but this is not my situation (pin usage saving, board design, etc.)
Only problem want I have unsolved is that, I have same configuration but i need two images - compressed and uncompressed. And this is needed only because JTAG accept uncompressed image but EPCS1 requires compressed one. I would like to do only one these operations
- compress image inside MCU or
- uncompress image inside MCU
to reduce two images to one only inside MCU.
I read patent US8,427,347 but it seems there is a much easier compression used by CYCLONE II.
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The second problem is: I'm unable to compile ENHANCED SFL into EP2C5 - the compiler is stopped with no warning or error [Quartus II 12.0sp2 Web Edition] and CPU load goest to 100%. If I unchecked ENHANCED SFL, the compiler works. But this is minority problem for me.
Petr
Honored Contributor
