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Altera_Forum
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18 years ago

Cyclone II and DDR pins

Hi In Cyclone II ep2c5 pinouts document: http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf Some pins have additional discription: DQxxx DQSxx DMxx. Why this DDR signals are assign...
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Altera_Forum
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18 years ago

You need to assign DQS/DQ lines to special S/Q pins because the FPGA logic (usually the ALTMEMPHY) needs to adjust the clock phase at the input buffers in order to capture the data correctly. Only S and Q pins have this capability.

DM lines, which are outputs (and all the other DDR lines for this matter), can be assigned to any pins as far as I am aware.