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Altera_Forum
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19 years ago

Cyclone II and DDR pins

Hi In Cyclone II ep2c5 pinouts document: http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf Some pins have additional discription: DQxxx DQSxx DMxx. Why this DDR signals are assign...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

I found information that DQS signals are assign to this pins because this pins are routed directly to the clock control block and global clock bus.

But I still don't know why DQx (data) and DM (data mask) signals are assign in this way.

This assignment is not comfortable for me but I don't know whether I can change it.

Any suggestion will be appreciate.

PGW